Programme of DCC

SATURDAY, March 27

9:00
9:40
A Hierarchical Modeling System
Warren A. Hunt, Jr. and Erik Reeber (University of Texas at Austin)
9:40
10:20
Wired - a Language for Describing Non-Functional Properties of Digital Circuits
Emil Axelsson, Koen Claessen, and Mary Sheeran (Chalmers University of Technology)
10:20
11:00
Coffee
11:00
10:40
Integrating Formal Methods with Digital Circuit Design in Hydra
John O'Donnell (University of Glasgow)
11:40
12:20
HML: A language for high-level design of high-frequency circuits
Andrew K. Martin (IBM)
12:20
14:00
Lunch
14:00
14:40
Late design changes (ECO) for sequentially optimized high-level designs
Laurent Arditi, Gérard Berry, and Michael Kishinevsky (Intel and Esterel Technologies)
14:40
15:20
Structure-Driven Equivalence Verification for Circuits Optimized by Retiming and Combinational Synthesis
Maher Mneimneh and Karem Sakallah (University of Michigan)
15:20
16:00
Coffee
16:00
16:40
A Reflective Functional Language for Hardware Design and Theorem Proving
Jim Grundy, Tom Melham, and John O'Leary (Intel and University of Oxford)
16:40
17:20
Verifying the ARM Block Data Transfer Instructions
Anthony Fox (University of Cambridge)

SUNDAY, March 28

9:00
9:40
satGSTE: Combining the Abstraction of GSTE with the Capacity of a SAT Solver
Jin Yang, Rami Gil, and Eli Singerman (Intel)
9:40
10:20
Symbolic Trajectory Evaluation using Satisfiability Solvers
Koen Claessen and Jan-Willem Roorda (Chalmers University of Technology)
10:20
11:00
Coffee
11:00
11:40
Verification of Parametric Timed Circuits using Octahedra
Robert Clarisó and Jordi Cortadella (Universitaat Politécnica de Catalunya)
11:40
12:20
Trading Completeness for Capacity using Probabilistic Techniques
René Krenz and Elena Dubrova (Royal Institute of Technology, Stockholm)
12:20
14:00
Lunch
14:00
14:40
Formal Verification of Floating Point Multiply Add on Itanium® Processor
Anna Slobodová and Krishna Nagalla (Intel)
14:40
15:20
The Post-Silicon Verification Problem: Designing Limited Observability Checkers for Shared Memory Processors
Ganesh Gopalakrishnan and Ching-Tsun Chou (University of Utah and Intel)
15:20
16:00
Coffee
16:00
16:40
An Operational Semantics for Safety PSL
Koen Claessen and Johan Mårtensson (Safelogic AB, Chalmers University of Technology, and Gothenburg University)
16:40
17:20
PSL semantics in higher order logic
Mike Gordon (University of Cambridge)
Evening
Pre-Conference Workshops Dinner