TaxoSynthesis is a CAD tool designed by a group of authors from Saint Petersburg (Russia) as a supplement for their research on the asynchronous control dominated circuits design.

It runs on PC with Microsoft Windows, supports file formats used by some other tools (among them Petrify) designed for asynchronous circuits synthesis and STG analysis and manipulation.

It can be used for specifying the model, checking and transforming the initial specification to the synthesizable form, simulating the behavior specified by STG as well as the resulting circuit behavior in VHDL environment and estimate the area, power consumption of the circuit obtained for the STG.

Since for a long while the tool has only been developed for the exclusive use of the authors it may be sometimes not that obvious or convenient for those not familiar with it. As well it may still suffer from some bugs. Therefore we would greatly appreciate any feedback on the tool you may have.