Publications in conferences


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[MRC17]
Lucas Machado, Antoni Roca, and Jordi Cortadella. Voltage noise analysis with ring oscillator clocks. In Proc. IEEE Computer Society Annual Symposium on VLSI, pages 86--95, July 2017. [ bib | PPT | PDF ]
[MCdG17]
Andrey Mokhov, Jordi Cortadella, and Alessandro de Gennaro. Process windows. In Int. Conf. on Application of Concurrency to System Design, pages 86--95, June 2017. [ bib | PPT | PDF ]
[CMS+17]
Jordi Cortadella, Alberto Moreno, Danil Sokolov, Alex Yakovlev, and David Lloyd. Waveform transition graphs: a designer-friendly formalism for asynchronous behaviours. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 73--74, May 2017. [ bib | PDF ]
[MC17b]
Alberto Moreno and Jordi Cortadella. Synthesis of all-digital delay lines. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 75--82, May 2017. [ bib | PDF ]
[VCP17]
Alex Vidal-Obiols, Jordi Cortadella, and Jordi Petit. Under-the-cell routing to improve manufacturability. In Proc. of the Great Lakes Symposium on VLSI, pages 125--130, May 2017. [ bib | PDF ]
[MC17a]
Lucas Machado and Jordi Cortadella. Boolean decomposition for AIG optimization. In Proc. of the Great Lakes Symposium on VLSI, pages 143--148, May 2017. [ bib | PDF ]
[MCR17]
Lucas Machado, Jordi Cortadella, and Antoni Roca. Increasing the robustness of digital circuits with ring oscillator clocks. In 2nd International Workshop on Resiliency in Embedded Electronic Systems (REES), March 2017. [ bib | PDF ]
[CLM+16]
Jordi Cortadella, Marc Lupon, Alberto Moreno, Antoni Roca, and Sachin S. Sapatnekar. Ring oscillator clocks and margins. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 19--26, May 2016. Best paper award. [ bib | PPT | PDF ]
[dSPBC16]
Javier de San Pedro, Thomas Bourgeat, and Jordi Cortadella. Specification mining of asynchronous controllers. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 107--114, May 2016. [ bib | PPT | PDF ]
[dSPC16b]
Javier de San Pedro and Jordi Cortadella. Mining structured petri nets for the visualization of process behavior. In 31st ACM Symposium on Applied Computing, pages 839--846, April 2016. [ bib | PPT | PDF ]
[dSPC16a]
Javier de San Pedro and Jordi Cortadella. Discovering duplicate tasks in transition systems for the simplification of process models. In Proc. 14th Int. Conf. Business Process Management, volume 9850 of Lecture Notes in Computer Science, pages 108--124. Springer-Verlag, 2016. [ bib | DOI | PDF ]
[CLL+15]
Jordi Cortadella, Luciano Lavagno, Pedro López, Marc Lupon, Alberto Moreno, Antoni Roca, and Sachin S. Sapatnekar. Reactive clocks with variability-tracking jitter. In Proc. International Conf. Computer Design (ICCD), pages 540--547, October 2015. [ bib | PPT | PDF ]
[dSPCC15]
Javier de San Pedro, Josep Carmona, and Jordi Cortadella. Log-based simplification of process models. In Proc. 13th Int. Conf. Business Process Management, volume 9253 of Lecture Notes in Computer Science, pages 457--474. Springer-Verlag, September 2015. [ bib | DOI | PDF ]
[JSC15]
Palkesh Jain, Sachin S. Sapatnekar, and Jordi Cortadella. A retargetable and accurate methodology for logic-ip-internal electromigration assessment. In Proc. of Asia and South Pacific Design Automation Conference, pages 346--351, January 2015. [ bib | PDF ]
[dSPCR14]
Javier de San Pedro, Jordi Cortadella, and Antoni Roca. A hierarchical approach for generating regular floorplans. In Proc. International Conf. Computer-Aided Design (ICCAD), pages 655--662, November 2014. [ bib | PDF ]
[BCC+14]
Salomon Beer, Marco Cannizzaro, Jordi Cortadella, Ran Ginosar, and Luciano Lavagno. Metastability in better-than-worst-case designs. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 101--102, May 2014. [ bib | PDF ]
[DSP+14]
Giorgos Dimitrakopoulos, Ioannis Seitanidis, Anastasios Psarras, Kostas M. Tsiouris, Pavlos M. Mattheakis, and Jordi Cortadella. Hardware primitives for the synthesis of multithreaded elastic systems. In Proc. Design, Automation and Test in Europe (DATE), pages 1--4, March 2014. [ bib | PDF ]
[dSPNCP13]
Javier de San Pedro, Nikita Nikitin, Jordi Cortadella, and Jordi Petit. Physical planning for the architectural exploration of large-scale chip multiprocessors. In Proc. of the IEEE/ACM International Symp. on Networks-on-Chip (NoCS), pages 1--2, April 2013. [ bib | PDF ]
[CdSPNP13]
Jordi Cortadella, Javier de San Pedro, Nikita Nikitin, and Jordi Petit. Physical-aware system-level design for tiled hierarchical chip multiprocessors. In Proc. International Symposium on Physical Design, pages 3--10, March 2013. [ bib | PDF ]
[NdSPCC12]
Nikita Nikitin, Javier de San Pedro, Josep Carmona, and Jordi Cortadella. Analytical performance modeling of hierarchical interconnect fabrics. In Proc. of the IEEE/ACM International Symp. on Networks-on-Chip (NoCS), pages 107--114, May 2012. [ bib | PDF ]
[dSPCCP12]
Javier de San Pedro, Josep Carmona, Jordi Cortadella, and Jordi Petit. Integrating formal verification in an online judge for e-learning logic circuit design. In Proc. ACM Technical Symp. on Computer Science Education (SIGCSE), pages 451--456, February 2012. [ bib | PDF ]
[NC12]
Nikita Nikitin and Jordi Cortadella. Static task mapping for tiled chip multiprocessors with multiple voltage islands. In 25th Int. Conf. on Architecture of Computing Systems (ARCS), pages 50--62, February 2012. [ bib | PDF | URL ]
[PPMC11]
Jordi Pérez-Puigdemont, Francesc Moll, and Jordi Cortadella. Measuring the tolerance of self-adaptive clocks to supply voltage noise. In 26th Conf. on Design of Circuits and Integrated Systems (DCIS), pages 399--404, November 2011. [ bib | PDF ]
[GOCK10]
Marc Galceran-Oms, Jordi Cortadella, and Mike Kishinevsky. Symbolic performance analysis of elastic systems. In Proc. International Conf. Computer-Aided Design (ICCAD), pages 778--785, November 2010. [ bib | PDF ]
[CC10]
Josep Carmona and Jordi Cortadella. Process mining meets abstract interpretation. In Proc. European Conference on Machine Learning and Principles and Practice of Knowledge Discovery in Databases (ECML PKDD), volume 6321 of Lecture Notes in Artificial Intelligence, pages 184--199. Springer-Verlag, September 2010. [ bib | PDF ]
[CGOK10]
Jordi Cortadella, Marc Galceran-Oms, and Mike Kishinevsky. Elastic systems. In Proc. 8th ACM/IEEE Int. Conf. on Formal Methods and Models for Codesign (MEMOCODE 2010), pages 149--158, July 2010. [ bib | PDF ]
[CLA+10]
Jordi Cortadella, Luciano Lavagno, Djavad Amiri, Jonàs Casanova, Carlos Macián, Ferran Martorell, Juan A. Moya, Luca Necchi, Danil Sokolov, and Emre Tuncer. Narrowing the margins with elastic clocks. In Proc. IEEE Int. Conf. on Integrated Circuit Design and Technology (ICICDT), pages 146--150, June 2010. [ bib | PDF ]
[NCC+10]
Nikita Nikitin, S. Chatterjee, Jordi Cortadella, Mike Kishinevsky, and Umit Ogras. Physical-aware link allocation and route assignment for chip multiprocessing. In Proc. 4th ACM/IEEE Int. Symp. on Networks-on-Chip (NOCS), pages 125--134, May 2010. [ bib | PDF ]
[GOCKB10]
Marc Galceran-Oms, Jordi Cortadella, Mike Kishinevsky, and Dmitry Bufistov. Automatic microarchitectural pipelining. In Proc. Design, Automation and Test in Europe (DATE), pages 961--964, April 2010. [ bib | PDF ]
[NC09]
Nikita Nikitin and Jordi Cortadella. A performance analytical model for Network-on-Chip with constant service time routers. In Proc. International Conf. Computer-Aided Design (ICCAD), pages 571--578, November 2009. [ bib | PDF ]
[CC09]
Jonàs Casanova and Jordi Cortadella. Multi-level clustering for clock skew optimization. In Proc. International Conf. Computer-Aided Design (ICCAD), pages 547--554, November 2009. [ bib | PDF ]
[CCK09]
Josep Carmona, Jordi Cortadella, and Mike Kishinevsky. Divide-and-conquer strategies for process mining. In Proc. 7th Int. Conf. Business Process Management, volume 5701 of Lecture Notes in Computer Science, pages 327--343. Springer-Verlag, September 2009. [ bib | DOI ]
[BCGO+09]
Dmitry Bufistov, Jordi Cortadella, Marc Galceran-Oms, Jorge Júlvez, and Mike Kishinevsky. Retiming and recycling for elastic systems with early evaluation. In Proc. ACM/IEEE Design Automation Conference, pages 288--291, July 2009. [ bib | PDF ]
[GOCK09]
Marc Galceran-Oms, Jordi Cortadella, and Mike Kishinevsky. Speculation in elastic systems. In Proc. ACM/IEEE Design Automation Conference, pages 292--295, July 2009. [ bib | PDF ]
[TCL09]
Emre Tuncer, Jordi Cortadella, and Luciano Lavagno. Enabling adaptability through elastic clocks. In Proc. ACM/IEEE Design Automation Conference, pages 8--10, July 2009. [ bib | PDF ]
[CJCK09]
Josep Carmona, Jorge Júlvez, Jordi Cortadella, and Mike Kishinevsky. Scheduling synchronous elastic designs. In Int. Conf. on Application of Concurrency to System Design, June 2009. Best paper award. [ bib | URL ]
[GOCKB09]
Marc Galceran-Oms, Jordi Cortadella, Mike Kishinevsky, and Dmitry Bufistov. Automatic microarchitectural pipelining. In Proc. International Workshop on Logic Synthesis, pages 214--221, June 2009. [ bib ]
[BCK09a]
David Bañeres, Jordi Cortadella, and Mike Kishinevsky. Timing-driven n-way decomposition. In Proc. of the Great Lakes Symposium on VLSI, pages 363--368, May 2009. [ bib | PDF ]
[BCK09b]
David Bañeres, Jordi Cortadella, and Mike Kishinevsky. Variable-latency design by function speculation. In Proc. Design, Automation and Test in Europe (DATE), pages 1704--1709, March 2009. [ bib | PDF ]
[BJC08]
Dmitry Bufistov, Jorge Júlvez, and Jordi Cortadella. Performance optimization of elastic systems using buffer resizing and buffer insertion. In Proc. International Conf. Computer-Aided Design (ICCAD), pages 442--448, November 2008. [ bib | PDF ]
[KKCGO08]
Timothy Kam, Mike Kishinevsky, Jordi Cortadella, and Marc Galceran-Oms. Correct-by-construction microarchitectural pipelining. In Proc. International Conf. Computer-Aided Design (ICCAD), pages 434--441, November 2008. [ bib | PDF ]
[GC08]
Kyller Gorgônio and Jordi Cortadella. Hardware synthesis for asynchronous communications mechanisms. In Int. Conf. of the Chilean Computer Science Society (SCCC), pages 135--143, November 2008. [ bib | PDF ]
[ZBC08]
Andrey Ziyatdinov, David Bañeres, and Jordi Cortadella. Multi-clustering net model for placement algorithms. In Proc. 16th IFIP/IEEE Int. Conf. on Very Large Scale Integration, October 2008. [ bib | PDF ]
[CCK08a]
Josep Carmona, Jordi Cortadella, and Mike Kishinevsky. A region-based algorithm for discovering Petri nets from event logs. In Proc. 6th Int. Conf. on Business Process Management (BPM), volume 5240 of Lecture Notes in Computer Science, pages 358--373. Springer-Verlag, September 2008. [ bib ]
[CCK+08b]
Josep Carmona, Jordi Cortadella, Mike Kishinevsky, Alex Kondratyev, Luciano Lavagno, and Alex Yakovlev. A symbolic algorithm for the synthesis of bounded Petri nets. In Applications and Theory of Petri Nets and Other Models of Concurrency (ICATPN), volume 5062 of Lecture Notes in Computer Science, pages 92--111. Springer-Verlag, June 2008. [ bib | DOI ]
[BCKS07]
Dmitry Bufistov, Jordi Cortadella, Mike Kishinevsky, and Sachin S. Sapatnekar. A general model for performance optimization of sequential systems. In Proc. International Conf. Computer-Aided Design (ICCAD), pages 362--369, November 2007. [ bib | PDF ]
[GCX07]
Kyller Gorgônio, Jordi Cortadella, and Fei Xia. A compositional method for the synthesis of asynchronous communication mechanisms. In Applications and Theory of Petri Nets and Other Models of Concurrency (ICATPN), volume 4546 of Lecture Notes in Computer Science, pages 144--163. Springer-Verlag, June 2007. [ bib | PDF ]
[CK07]
Jordi Cortadella and Mike Kishinevsky. Synchronous elastic circuits with early evaluation and token counterflow. In Proc. ACM/IEEE Design Automation Conference, pages 416--419, June 2007. [ bib | PDF ]
[BCK07]
David Bañeres, Jordi Cortadella, and Mike Kishinevsky. Layout-aware gate duplication and buffer insertion. In Proc. Design, Automation and Test in Europe (DATE), pages 1367--1372, April 2007. [ bib | PDF ]
[KCKO06a]
Sava Krstić, Jordi Cortadella, Mike Kishinevsky, and John O'Leary. Synchronous elastic networks. In International Conference on Formal Methods in Computer-Aided Design (FMCAD), November 2006. [ bib | PDF ]
[CCTP06]
Josep Carmona, Jordi Cortadella, Yousuke Takada, and Ferdinand Peper. From molecular interactions to gates: a systematic approach. In Proc. International Conf. Computer-Aided Design (ICCAD), November 2006. [ bib | PDF ]
[JCK06]
Jorge Júlvez, Jordi Cortadella, and Mike Kishinevsky. Performance analysis of concurrent systems with early evaluation. In Proc. International Conf. Computer-Aided Design (ICCAD), November 2006. [ bib | PDF ]
[CC06]
Josep Carmona and Jordi Cortadella. State encoding of large asynchronous controllers. In Proc. ACM/IEEE Design Automation Conference, pages 939--944, July 2006. [ bib | PPT | PDF ]
[CKG06b]
Jordi Cortadella, Mike Kishinevsky, and Bill Grundmann. Synthesis of synchronous elastic architectures. In Proc. ACM/IEEE Design Automation Conference, pages 657--662, July 2006. [ bib | PPT | PDF ]
[BCK06]
David Bañeres, Jordi Cortadella, and Mike Kishinevsky. Dominator-based partitioning for delay optimization. In Proc. of the Great Lakes Symposium on VLSI, pages 67--72, April 2006. [ bib | PDF ]
[KCKO06b]
Sava Krstić, Jordi Cortadella, Mike Kishinevsky, and John O'Leary. Synchronous elastic networks. In Mary Sheeran and Tom Melham, editors, Sixth International Workshop on Designing Correct Circuits (DCC). ETAPS 2006, March 2006. [ bib ]
[CKG06a]
Jordi Cortadella, Mike Kishinevsky, and Bill Grundmann. Specification and design of synchronous elastic circuits. In Proc. International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pages 16--21, February 2006. [ bib | PDF ]
[CC05]
Robert Clarisó and Jordi Cortadella. Verification of concurrent systems with parametric delays using octahedra. In Int. Conf. on Application of Concurrency to System Design, pages 122--131, June 2005. [ bib | PDF ]
[CGXY05]
Jordi Cortadella, Kyller Gorgônio, Fei Xia, and Alex Yakovlev. Automatic synthesis of asynchronous coomunication mechanisms. In Int. Conf. on Application of Concurrency to System Design, pages 166--175, June 2005. [ bib | PDF ]
[CRCC05]
Robert Clarisó, Enric Rodríguez-Carbonell, and Jordi Cortadella. Derivation of non-structural invariants of Petri nets using abstract interpretation. In Application and Theory of Petri Nets 2004, volume 3536 of Lecture Notes in Computer Science, pages 188--207. Springer-Verlag, June 2005. [ bib | PDF ]
[RCC05]
Enric Rodríguez-Carbonell and Jordi Cortadella. Inference of numerical relations from digital circuits. Extended abstract of the presentation at the First International Workshop on Numerical & Symbolic Abstract Domains (NSAD), January 2005. [ bib | PDF ]
[CKLS04]
Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, and Christos P. Sotiriou. Coping with the variability of combinational logic delays. In Proc. International Conf. Computer Design (ICCD), pages 505--508, October 2004. [ bib | PDF ]
[CC04a]
Robert Clarisó and Jordi Cortadella. The octahedron abstract domain. In 11th Static Analysis Symposium (SAS), volume 3148 of Lecture Notes in Computer Science, pages 312--327. Springer-Verlag, August 2004. [ bib | PDF ]
[BCK04a]
D. Bañeres, Jordi Cortadella, and Mike Kishinevsky. A recursive paradigm to solve boolean relations. In Proc. ACM/IEEE Design Automation Conference, pages 416--421, June 2004. Best paper award. [ bib | PPT | PDF ]
[BCK+04b]
Ivan Blunno, Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Kelvin Lwin, and Christos P. Sotiriou. Handshake protocols for de-synchronization. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 149--158, April 2004. Best paper award. [ bib | PPT | PDF ]
[CKL+04]
Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Kelvin Lwin, and Christos P. Sotiriou. From synchronous to asynchronous: An automatic approach. In Proc. Design, Automation and Test in Europe (DATE), volume 2, pages 1368--1369, February 2004. [ bib | PDF ]
[CC04b]
Robert Clarisó and Jordi Cortadella. Verification of timed circuits with symbolic delays. In Proc. of Asia and South Pacific Design Automation Conference, pages 628--633, January 2004. [ bib | PDF ]
[MC04]
Nilesh Modi and Jordi Cortadella. Boolean decomposition using two-literal divisors. In Proc. International Conference on VLSI Design, January 2004. [ bib | PDF ]
[CC03a]
Josep Carmona and Jordi Cortadella. ILP models for the synthesis of asynchronous control circuits. In Proc. International Conf. Computer-Aided Design (ICCAD), pages 818--825, November 2003. [ bib | PDF ]
[CKLW03]
Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, and Yosinori Watanabe. Quasi-static scheduling for concurrent architectures. In Int. Conf. on Application of Concurrency to System Design, pages 29--40, June 2003. [ bib | PDF ]
[CKLS03]
Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, and Christos P. Sotiriou. A concurrent model for de-synchronization. In Proc. International Workshop on Logic Synthesis, pages 294--301, May 2003. [ bib | PDF ]
[CC03b]
Robert Clarisó and Jordi Cortadella. Verification of timed circuits with symbolic delays. In Proc. International Workshop on Logic Synthesis, pages 310--317, May 2003. [ bib | PDF ]
[CC02]
Josep Carmona and Jordi Cortadella. Input/output compatibility of reactive systems. In M. Aagaard and J.W. O'Leary, editors, International Conference on Formal Methods in Computer-Aided Design (FMCAD), volume 2517 of Lecture Notes in Computer Science, pages 360--377. Springer-Verlag, November 2002. [ bib | PDF ]
[CKL+02]
Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Claudio Passerone, and Yosinori Watanabe. Quasi-static scheduling of independent tasks for reactive systems. In Application and Theory of Petri Nets 2002, volume 2360 of Lecture Notes in Computer Science, pages 80--99. Springer-Verlag, June 2002. [ bib | PS ]
[Cor02]
Jordi Cortadella. Bi-decomposition and tree-height reduction for timing optimization. In Proc. International Workshop on Logic Synthesis, June 2002. [ bib | PDF ]
[CCK+02]
Robert Clarisó, Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Claudio Passerone, and Yosinori Watanabe. Synthesis of embedded software for reactive systems. In Int. Workshop on Integration of Specification Techniques for Applications in Engineering (Satellite event of ETAPS 2002), pages 2--20, April 2002. [ bib | PS ]
[PCPS02]
Marco A. Peña, Jordi Cortadella, Enric Pastor, and A. Smirnov. A case study for the verification of complex timed circuits: IPCMOS. In Proc. Design, Automation and Test in Europe (DATE), pages 44--51, March 2002. [ bib | PDF ]
[CC01a]
G. Cornetta and Jordi Cortadella. Asynchronous multipliers with variable-delay counters. In 8th IEEE Int. Conf. on Electronics, Circuits and Systems (ICECS), volume II, pages 701--705, September 2001. [ bib | PDF ]
[CCP01]
Josep Carmona, Jordi Cortadella, and Enric Pastor. A structural encoding technique for the synthesis of asynchronous circuits. In Int. Conf. on Application of Concurrency to System Design, pages 157--166, June 2001. [ bib | PDF ]
[CC01b]
Gianluca Cornetta and Jordi Cortadella. A multi-radix approach to asynchronous division. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 25--34, March 2001. [ bib | PDF ]
[CKK+00]
Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, and Alexandre Yakovlev. Hardware and Petri nets: Application to asynchronous circuit design. In Application and Theory of Petri Nets 2000, volume 1825 of Lecture Notes in Computer Science, pages 1--15. Springer-Verlag, June 2000. [ bib | PS ]
[CKL+00]
Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Marc Massot, Sandra Moral, Claudio Passerone, Yosinori Watanabe, and Alberto Sangiovanni-Vincentelli. Task generation and compile-time scheduling for mixed data-control embedded software. In Proc. ACM/IEEE Design Automation Conference, pages 489--494, June 2000. [ bib | PDF ]
[PCKP00]
Marco A. Peña, Jordi Cortadella, Alex Kondratyev, and Enric Pastor. Formal verification of safety properties in timed circuits. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 2--11, April 2000. [ bib | PDF ]
[CV00]
Jordi Cortadella and Gabriel Valiente. A relational view of subgraph isomorphism. In Proc. International Seminar on Relational Methods in Computer Science, pages 45--54, January 2000. [ bib | PDF ]
[SKC+99b]
Hiroshi Saito, Alex Kondratyev, Jordi Cortadella, Luciano Lavagno, and Alexander Yakovlev. What is the cost of delay insensitivity? In Proc. International Conf. Computer-Aided Design (ICCAD), pages 316--323, November 1999. [ bib | PDF ]
[CKBS99]
Jordi Cortadella, Michael Kishinevsky, Steven M. Burns, and Ken Stevens. Synthesis of asynchronous control circuits with automatically generated timing assumptions. In Proc. International Conf. Computer-Aided Design (ICCAD), pages 324--331, November 1999. [ bib | PDF ]
[SKC+99a]
Hiroshi Saito, Alex Kondratyev, Jordi Cortadella, Luciano Lavagno, and Alexander Yakovlev. Bridging modularity and optimality: delay-insensitive interfacing in asynchronous circuits synthesis. In Proc. IEEE International Conference on Systems, Man and Cybernetics (SMC), volume 3, pages 899--904, October 1999. [ bib | PDF ]
[PCP99]
Enric Pastor, Jordi Cortadella, and Marco A. Peña. Structural Methods to Improve the Symbolic Analysis of Petri Nets. In Application and Theory of Petri Nets 1999, volume 1639 of Lecture Notes in Computer Science, pages 26--45. Springer-Verlag, June 1999. [ bib | PS ]
[SRB+99]
Ken Stevens, Shai Rotem, Steven M. Burns, Jordi Cortadella, Ran Ginosar, Michael Kishinevsky, and Marly Roncken. CAD directions for high performance asynchronous circuits. In Proc. ACM/IEEE Design Automation Conference, pages 116--121, June 1999. [ bib | PDF ]
[KCK+99]
Alex Kondratyev, Jordi Cortadella, Michael Kishinevsky, Luciano Lavagno, and Alexander Yakovlev. Automatic synthesis and optimization of partially specified asynchronous systems. In Proc. ACM/IEEE Design Automation Conference, pages 110--115, June 1999. [ bib | PDF ]
[SKC+99c]
Hiroshi Saito, Alex Kondratyev, Jordi Cortadella, Luciano Lavagno, and Alexander Yakovlev. What is the cost of delay insensitivity? In Proc. of the Workshop Hardware Design and Petri Nets (within the International Conference on Application and Theory of Petri Nets), pages 169--189, June 1999. [ bib ]
[TKCL99a]
A. Taubin, Alex Kondratyev, Jordi Cortadella, and Luciano Lavagno. Behavioral transformations to increase the noise immunity of asynchronous specifications. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 36--47, April 1999. [ bib | PDF ]
[CC99]
Gianluca Cornetta and Jordi Cortadella. A radix-16 SRT division unit with speculation of quotient digits. In Proc. of the Great Lakes Symposium on VLSI, pages 74--77, March 1999. [ bib | PDF ]
[TKCL99b]
A. Taubin, Alex Kondratyev, Jordi Cortadella, and Luciano Lavagno. Crosstalk noise avoidance in asynchronous circuits. In Proc. International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pages 123--128, March 1999. [ bib | PS ]
[CKK+98b]
Jordi Cortadella, Mike Kishinevsky, Alex Kondratyev, Luciano Lavagno, A. Taubin, and Alex Yakovlev. Lazy transition systems: application to timing optimization of asynchronous circuits. In Proc. International Conf. Computer-Aided Design (ICCAD), pages 324--331, November 1998. [ bib | PDF ]
[LMC98]
Tomás Lang, Enric Musoll, and Jordi Cortadella. Extension of the working-zone-encoding method to reduce also the energy on the microprocessor data bus. In Proc. International Conf. Computer Design (ICCD), pages 414--419, October 1998. [ bib | PDF ]
[KCK98a]
Mike Kishinevsky, Jordi Cortadella, and Alex Kondratyev. Asynchronous interface specification, analysis and synthesis. In Proc. ACM/IEEE Design Automation Conference, pages 2--7, June 1998. [ bib | PDF ]
[CKK+98a]
Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, and Alexandre Yakovlev. Automatic handshake expansion and reshuffling using concurrency reduction. In Proc. of the Workshop Hardware Design and Petri Nets (within the International Conference on Application and Theory of Petri Nets), pages 86--110, June 1998. [ bib | PS ]
[PC98b]
Enric Pastor and Jordi Cortadella. Structural methods applied to the symbolic analysis of Petri nets. In Proc. International Workshop on Logic Synthesis, June 1998. [ bib ]
[MLC98]
Enric Musoll, Tomás Lang, and Jordi Cortadella. Reducing the energy of address and data buses with the working-zone encoding technique and its effect on multimedia applications. In Proc. of the Power Driven Microarchitecture Workshop, pages 3--8, June 1998. [ bib | PS ]
[Cor98]
Jordi Cortadella. Combining structural and symbolic methods for the verification of concurrent systems. In Int. Conf. on Application of Concurrency to System Design, pages 2--7, March 1998. [ bib | PDF ]
[KCK+98b]
Alex Kondratyev, Jordi Cortadella, Mike Kishinevsky, Luciano Lavagno, A. Taubin, and Alex Yakovlev. Identifying state coding conflicts in asynchronous system specifications using Petri net unfoldings. In Int. Conf. on Application of Concurrency to System Design, pages 152--163, March 1998. [ bib | PDF ]
[PC98a]
Enric Pastor and Jordi Cortadella. Efficient encoding schemes for symbolic analysis of Petri nets. In Proc. Design, Automation and Test in Europe (DATE), pages 790--795, March 1998. [ bib | PDF ]
[CKK+97a]
Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Enric Pastor, and Alexandre Yakovlev. Decomposition and technology mapping of speed-independent circuits using Boolean relations. In Proc. International Conf. Computer-Aided Design (ICCAD), November 1997. [ bib | PDF ]
[MLC97]
Enric Musoll, Tomás Lang, and Jordi Cortadella. Exploiting the locality of memory references to reduce the address bus energy. In International Symposium on Low Power Electronics and Design, pages 202--207, August 1997. [ bib | PDF ]
[KCK+97]
Michael Kishinevsky, Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Alexander Taubin, and Alex Yakovlev. Coupling asynchrony and interrupts: Place chart nets and their synthesis. In Pierre Azéma and Gianfranco Balbo, editors, Application and Theory of Petri Nets 1997, volume 1248 of Lecture Notes in Computer Science, pages 328--347. Springer-Verlag, Toulouse, France, June 1997. [ bib ]
[RCPP97]
Oriol Roig, Jordi Cortadella, Marco A. Peña, and Enric Pastor. Automatic generation of synchronous test patterns for asynchronous circuits. In Proc. ACM/IEEE Design Automation Conference, pages 620--625, June 1997. [ bib | PDF ]
[SYP+97a]
Alex Semenov, Alexandre Yakovlev, Enric Pastor, Marco A. Peña, and Jordi Cortadella. Synthesis of speed-independent circuits from STG-unfolding segment. In Proc. ACM/IEEE Design Automation Conference, pages 16--21, June 1997. [ bib | PDF ]
[CLS97]
Jordi Cortadella, Luciano Lavagno, and Ellen Sentovich. Logic synthesis techniques for embedded control code optimization. In Proc. International Workshop on Logic Synthesis, June 1997. [ bib ]
[SYP+97b]
Alex Semenov, Alexandre Yakovlev, Enric Pastor, Marco A. Peña, Jordi Cortadella, and Luciano Lavagno. Partial order based approach to synthesis of speed-independent circuits. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 254--265. IEEE Computer Society Press, April 1997. [ bib | PDF ]
[KKC+97]
Alex Kondratyev, Michael Kishinevsky, Jordi Cortadella, Luciano Lavagno, and Alex Yakovlev. Technology mapping for speed-independent circuits: decomposition and resynthesis. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 240--253. IEEE Computer Society Press, April 1997. [ bib | PDF ]
[LCSV97]
Luciano Lavagno, Jordi Cortadella, and Alberto Sangiovanni-Vincentelli. Embedded code optimization via common control structure detection. In International Workshop on Hardware/Software Co-Design (Codes/CASHE), March 1997. [ bib ]
[CKK+97b]
Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, and Alex Yakovlev. Technology mapping of speed-independent circuits based on combinational decomposition and resynthesis. In Proc. European Design and Test Conference, pages 98--105, 1997. [ bib | PDF ]
[CKK+96b]
Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, and Alexandre Yakovlev. Petrify: a tool for manipulating concurrent specifications and synthesis of asynchronous controllers. In XI Conference on Design of Integrated Circuits and Systems, pages 205--210, Barcelona, November 1996. [ bib | PS ]
[LMC96]
Tomás Lang, Enric Musoll, and Jordi Cortadella. Redundant adder for reduced output transitions. In XI Conference on Design of Integrated Circuits and Systems, pages 17--22, Barcelona, November 1996. [ bib | PS ]
[CBS96]
Jordi Cortadella, Rosa M. Badia, and Fermín Sánchez. A mathematical formulation of the loop pipelining problem. In XI Conference on Design of Integrated Circuits and Systems, pages 355--360, Barcelona, November 1996. [ bib | PS ]
[SEP+96]
L. Sintes, J. Escudero, M.A. Peña, Oriol Roig, J. Cortadella, and J. Carrabina. Flujo de diseño asíncrono con la biblioteca DCVSL_LIB para ES2 ECPD10. In Actas del II Congreso sobre Tecnologías Aplicadas a la Enseñanza de la Electrónica, pages 161--166, Sevilla, September 1996. [ bib ]
[SC96b]
Fermín Sánchez and Jordi Cortadella. RESIS: A new methodology for register optimization in software pipelining. In Proc. European Conference on Parallel Processing (EURO-PAR), August 1996. [ bib | PS ]
[SC96a]
Fermín Sánchez and Jordi Cortadella. Maximum-throughput software pipelining. In Proc. International Conference on Massively Parallel Computing Systems, pages 483--490, May 1996. [ bib | PDF ]
[PC96]
Marco A. Peña and Jordi Cortadella. Combining process algebras and Petri nets for the specification and synthesis of asynchronous circuits. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems. IEEE Computer Society Press, March 1996. [ bib | PDF ]
[MC96]
Enric Musoll and Jordi Cortadella. Optimizing CMOS circuits for low power using transistor reordering. In Proc. European Design and Test Conference, pages 222--232, March 1996. [ bib | PDF ]
[PCRK96]
Enric Pastor, Jordi Cortadella, Oriol Roig, and Alex Kondratyev. Structural methods for the synthesis of speed-independent circuits. In Proc. European Design and Test Conference, pages 340--347. IEEE Computer Society Press, March 1996. [ bib | PDF ]
[CKK+96c]
Jordi Cortadella, Mike Kishinevsky, Alex Kondratyev, Luciano Lavagno, and Alex Yakovlev. Complete state encoding based on the theory of regions. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems. IEEE Computer Society Press, March 1996. [ bib | PDF ]
[CKK+96a]
Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, and Alex Yakovlev. Methodology and tools for state encoding in asynchronous circuit synthesis. In Proc. ACM/IEEE Design Automation Conference, 1996. [ bib | PDF ]
[PC95a]
Enric Pastor and Jordi Cortadella. Cover approximations for the synthesis of speed-independent circuits. In Proc. of the IFIP International Workshop on Logic and Architecture Synthesis, pages 150--159, December 1995. [ bib | PS ]
[PC95b]
Marco A. Peña and Jordi Cortadella. Programación VLSI y síntesis de circuitos asíncronos mediante composición de redes de Petri. In Actas del X Congreso de Diseño de Cirtuios Integrados y Sistemas, pages 65--70, Zaragoza, November 1995. [ bib | PS ]
[SC95]
Fermín Sánchez and Jordi Cortadella. Time constrained loop pipelining. In Proc. International Conf. Computer-Aided Design (ICCAD), pages 592--596, November 1995. [ bib | PDF ]
[MC95b]
Enric Musoll and Jordi Cortadella. Low-power array multipliers with transition-retaining barriers. In Power and Timing Modeling, Optimization and Simulation (PATMOS), pages 227--238, October 1995. [ bib | PS ]
[MC95c]
Enric Musoll and Jordi Cortadella. Scheduling and resource binding for low power. In International Symposium on System Synthesis, pages 104--109, September 1995. [ bib | PDF ]
[RCP95b]
Oriol Roig, Jordi Cortadella, and Enric Pastor. Verification of asynchronous circuits by BDD-based model checking of Petri nets. In Application and Theory of Petri Nets 1995, volume 815 of Lecture Notes in Computer Science, pages 374--391. Springer-Verlag, June 1995. [ bib | PS ]
[RCP95a]
Oriol Roig, Jordi Cortadella, and Enric Pastor. Hierarchical gate-level verification of speed-independent circuits. In Asynchronous Design Methodologies, pages 129--137. IEEE Computer Society Press, May 1995. [ bib | PDF ]
[MC95a]
Enric Musoll and Jordi Cortadella. High-level synthesis techniques for reducing the activity of functional units. In International Symposium on Low Power Design, pages 94--104, April 1995. [ bib | PS ]
[PCR95]
Enric Pastor, Jordi Cortadella, and Oriol Roig. A new look at the conditions for the synthesis of speed-independent circuits. In Proc. of the Great Lakes Symposium on VLSI, pages 230--235, March 1995. [ bib | PDF ]
[KCK+95]
Alex Kondratyev, Jordi Cortadella, Mike Kishinevsky, Enric Pastor, Oriol Roig, and Alex Yakovlev. Checking Signal Transition Graph implementability by symbolic BDD traversal. In Proc. European Design and Test Conference, pages 325--332, Paris, France, March 1995. [ bib | PDF ]
[CKLY95]
Jordi Cortadella, Mike Kishinevsky, Luciano Lavagno, and Alex Yakovlev. Synthesizing Petri nets from state-based models. In Proc. International Conf. Computer-Aided Design (ICCAD), pages 164--171, 1995. [ bib | PDF ]
[CLVY94]
Jordi Cortadella, Luciano Lavagno, Peter Vanbekbergen, and Alexandre Yakovlev. Designing asynchronous circuits from behavioral specifications with internal conflicts. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 106--115, November 1994. [ bib | PDF ]
[RPC94]
Oriol Roig, Enric Pastor, and Jordi Cortadella. Verificación de circuitos independientes de la velocidad con modelos simbólicos de redes de Petri. In Actas del IX Congreso de Diseño de Cirtuios Integrados y Sistemas, pages 307--312, Gran Canaria, November 1994. [ bib | PS ]
[PRCB94]
Enric Pastor, Oriol Roig, Jordi Cortadella, and Rosa M. Badia. Petri net analysis using boolean manipulation. In Application and Theory of Petri Nets 1994, volume 815 of Lecture Notes in Computer Science, pages 416--435. Springer-Verlag, June 1994. [ bib | PS ]
[CFL94]
Jordi Cortadella, J.A.B. Fortes, and E.A. Lee. Design and prototyping of digital signal processing systems (minitrack introduction). In Proc. Hawaii International Conf. System Sciences, pages 56--57, January 1994. [ bib ]
[PC93b]
Enric Pastor and Jordi Cortadella. Polynomial algorithms for the synthesis of hazard-free circuits from signal transition graphs. In Proc. International Conf. Computer-Aided Design (ICCAD), pages 250--254. IEEE Computer Society Press, November 1993. [ bib | PDF ]
[RPBC93]
Oriol Roig, Enric Pastor, Rosa M. Badia, and Jordi Cortadella. Síntesis de máquinas de control para circuitos asíncronos. In Actas del VIII Congreso de Diseño de Cirtuios Integrados y Sistemas, pages 326--331, Málaga, November 1993. [ bib | PS ]
[PC93a]
Enric Pastor and Jordi Cortadella. An efficient unique state coding algorithm for signal transition graphs. In Proc. International Conf. Computer Design (ICCD), pages 174--177, October 1993. [ bib | PDF ]
[CL93]
Jordi Cortadella and Tomás Lang. Division with speculation of quotient digits. In International Symposium on Computer Arithmetic, pages 87--94, June 1993. [ bib | PDF ]
[BC93]
Rosa M. Badia and Jordi Cortadella. High-level synthesis of asynchronous systems: Scheduling and process synchronization. In Proc. European Conference on Design Automation (EDAC), pages 70--74. IEEE Computer Society Press, February 1993. [ bib | PDF ]
[CBPP92a]
Jordi Cortadella, Rosa M. Badia, Enric Pastor, and Abelardo Pardo. Achilles: A high-level synthesis system for asynchronous circuits. In 6th ACM/IEEE International Workshop on High-Level Synthesis, pages 87--94, November 1992. [ bib | PS ]
[CBPP92b]
Jordi Cortadella, Rosa M. Badia, Enric Pastor, and Abelardo Pardo. Achilles: Sistema de síntesis de alto nivel para circuitos asíncronos. In Actas del VII Congreso de Diseño de Cirtuios Integrados y Sistemas, pages 357--362, Toledo, November 1992. [ bib ]
[CB92]
Jordi Cortadella and R. M. Badia. An asynchronous architecture model for behavioral synthesis. In Proc. European Conference on Design Automation (EDAC), pages 307--311. IEEE Computer Society Press, March 1992. [ bib | PDF ]
[BC91]
Rosa M. Badia and Jordi Cortadella. Optimización del tiempo de ciclo en la planificación de operaciones. In Actas del VI Congreso de Diseño de Cirtuios Integrados y Sistemas, pages 275--280, Santander, November 1991. [ bib ]
[WCN91]
G.S. Whitcomb, Jordi Cortadella, and A.R. Newton. Functional level synthesis of the TRISC processor. In IFIP International Workshop on Application of Synthesis and Simulation, August 1991. [ bib ]
[CBA91]
Jordi Cortadella, Rosa M. Badia, and Eduard Ayguadé. Scheduling in a continuous area-time design space: A simulated-annealing-based approach. In 5th ACM/IEEE International Workshop on High-Level Synthesis, pages 102--117, March 1991. [ bib ]
[BCA91]
Rosa M. Badia, Jordi Cortadella, and Eduard Ayguadé. Computer-aided synthesis of data-path by using a simulated-annealing-based approach. In 9th IAESTED International Symposium on Applied Informatics, pages 326--329, February 1991. [ bib ]
[CL88]
Jordi Cortadella and José M. Llabería. Evaluating A+B=K conditions in constant time. In Proc. International Symposium on Circuits and Systems, pages 243--246, June 1988. [ bib | PDF ]
[CJ88]
Jordi Cortadella and Teodor Jové. Executing zero-delay branches with a branch target buffer in a RISC processor. In 36th International Symposium on Mini and Microcomputers and their applications, pages 373--376, June 1988. [ bib ]
[DLVC88]
Jordi Domingo, José M. Llabería, Mateo Valero, and Jordi Cortadella. Arbitration techniques for packet switching multistage networks. In 3rd. International Conference on Supercomputing, volume III, pages 240--248, May 1988. [ bib ]
[Cor88]
Jordi Cortadella. Executing branch instructions with zero time delay in a RISC. In IEEE Computer Society Workshop on VLSI, Clearwater Beach (Florida), February 1988. [ bib ]
[GLC88]
Antonio González, José M. Llabería, and Jordi Cortadella. Zero-delay cost branches in RISC architectures. In 6th International Symposium on Applied Informatics, pages 24--27, February 1988. [ bib ]
[DLCV87]
Jordi Domingo, José M. Llabería, Jordi Cortadella, and Mateo Valero. Arbitration methods to increase the throughput of packed switching buffered shuffle-exchange interconnection networks. In International Symposium on Applied Informatics, pages 78--81, February 1987. [ bib ]
[CL87b]
Jordi Cortadella and José M. Llabería. An intelligent IFU for pipelined processors that makes control instructions transparent to the execution unit. In International Symposium on Applied Informatics, pages 188--191, February 1987. [ bib ]
[CL87c]
Jordi Cortadella and José M. Llabería. A low cost evaluation methodology for new architectures. In International Symposium on Applied Informatics, pages 188--191, February 1987. [ bib ]
[CL87a]
Jordi Cortadella and José M. Llabería. Arquitecturas RISC. In IV Jornadas de Diseño Lógico, pages 19--27, Barcelona, 1987. [ bib ]
[CL87d]
Jordi Cortadella and José M. Llabería. Procesadores RISC. In 1er. Seminario del grupo temático de Arquitectura y Tecnología de Ordenadores sobre Arquitecturas Multiprocesadores y sus Aplicaciones, Madrid, January 1987. [ bib ]
[GCL85]
Luis González, Jordi Cortadella, and José M. Llabería. Performance evaluation of a loosely coupled multiprocessor architecture with two buses. In International Symposium on Mini and Microcomputers and their applications, pages 473--476, June 1985. [ bib ]

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